1. Field of the Invention
This invention generally relates to methods and systems for metrology optimized inspection in which metrology data for a wafer is used to alter one or more parameters of a wafer inspection process for the wafer or another wafer.
2. Description of the Related Art
The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.
Fabricating semiconductor devices such as logic and memory devices typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing, etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a single semiconductor wafer and then separated into individual semiconductor devices.
Inspection processes are used at various steps during a semiconductor manufacturing process to detect defects on wafers. Inspection processes have always been an important part of fabricating semiconductor devices such as integrated circuits. However, as the dimensions of semiconductor devices decrease, inspection processes become even more important to the successful manufacture of acceptable semiconductor devices. For instance, as the dimensions of semiconductor devices decrease, detection of defects of decreasing size has become necessary since even relatively small defects may cause unwanted aberrations in the semiconductor devices.
Many different types of inspection systems have adjustable output acquisition (e.g., data, signal, and/or image acquisition) and sensitivity (or defect detection) parameters such that different parameters can be used to detect different defects or avoid sources of unwanted (nuisance) events. Although an inspection system that has adjustable output acquisition and sensitivity parameters presents significant advantages to a semiconductor device manufacturer, these inspection systems are essentially useless if the incorrect output acquisition and sensitivity parameters are used for an inspection process. Although using the correct output acquisition and sensitivity parameters will have a dramatic effect on the results of inspection, it is conceivable that many inspection processes are currently being performed with incorrect or non-optimized output acquisition and sensitivity parameters.
In currently used methods for wafer inspection process setup, a defect engineer may set up a wafer inspection recipe with several limitations. For example, the user may set up the inspection sensitivity based on a limited number of wafers that are available and only selected areas on the wafers. A user also may choose to use multiple wafers to set up sensitivity in an effort to accommodate wafer-to-wafer variation due to fabrication process variability. In other applications, a user may choose data from one or more die to define reference (nominal) images for the purpose of setting up a reference die. In such applications, a user can guess the best place to collect data but that place may not represent true nominal conditions. In another application, a user may choose various defects for review sampling but the sampling population is based on die or locations where the noise level is often unknown.
In the area of inspection optimization, not knowing where the noisy areas are can result in setting up sensitivity based on only noisy regions or only quiet regions that may not truly reflect variations across wafers. If die row selection was done on a quiet region, additional nuisance defects may arise when additional wafers are scanned. If die selection was done in a noisy region, real defects may be missed during production wafer scans due to thresholds being set too high. With respect to nominal die selection, the challenge is to select dies that are at truly nominal conditions where average thickness, critical dimension (CD), etc. are present. Not having this data set can lead to selecting dies that do not represent the nominal signature. With regard to defect sampling, defects that are sampled in a noisy region can produce low signal-to-noise while an optimized sampling from a quiet region may yield more real defects.
Accordingly, it would be advantageous to develop systems and/or methods that do not have one or more of the disadvantages described above.